JPS6457643U - - Google Patents
Info
- Publication number
- JPS6457643U JPS6457643U JP1987150142U JP15014287U JPS6457643U JP S6457643 U JPS6457643 U JP S6457643U JP 1987150142 U JP1987150142 U JP 1987150142U JP 15014287 U JP15014287 U JP 15014287U JP S6457643 U JPS6457643 U JP S6457643U
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- integrated circuit
- simulated
- mounting structure
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987150142U JPS6457643U (en]) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987150142U JPS6457643U (en]) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457643U true JPS6457643U (en]) | 1989-04-10 |
Family
ID=31423015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987150142U Pending JPS6457643U (en]) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457643U (en]) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE39603E1 (en) | 1994-09-30 | 2007-05-01 | Nec Corporation | Process for manufacturing semiconductor device and semiconductor wafer |
-
1987
- 1987-09-30 JP JP1987150142U patent/JPS6457643U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE39603E1 (en) | 1994-09-30 | 2007-05-01 | Nec Corporation | Process for manufacturing semiconductor device and semiconductor wafer |
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